Bart Vandevelde

How to deal with chip-package, package-board and board-system interactions for future electronic systems reliability

10 May 2019, 14:20-15:00

ICs that easily pass the wafer-level qualification testing do physically or electrically fail once they are packaged, components fail only when they are soldered to the PCB and full PCB assemblies passing board level reliability testing show early field failures when they are installed in a system box. The main reason is what we call the thermal and mechanical interaction between the different design layers: IC – component – PCB – system. This mechanical interaction becomes more dominant due to shorter and less flexible interconnections for more advanced applications. This talk will show, through practical cases, the challenges and methodologies in design and testing to avoid reliability issues due to mechanical interactions.

Bart Vandevelde has an MSc and PhD in mechanical engineering from KU Leuven. His main background is in thermomechanical simulation and experiments at package, PCB and electronic system level with a career of almost 25 years at Imec. He is currently the R&D project leader within the Electronic Assembly group of Imec responsible for research and consultancy projects. He has more than 200 papers as (co-)author in the field of thermomechanical reliability for electronics. He is a co-founder and member of the organization committee of the EuroSimE IEEE conference.